The present invention relates to a semiconductor device to which chip-size packaging using bumps is applied, as well as to a method for manufacturing the semiconductor device.
Various types of packaging structures for a semiconductor chip have been put forward. For instance, in association with miniaturization of a package, there has been proposed a structure called a chip-size package in which rewiring (wiring for packaging purpose) is routed on a passivation layer (a protective layer) of a device fabrication plane of a semiconductor chip.
In connection with the chip-size package, there has been put forth; for example, a method for forming a package (a semiconductor device) by means of forming bumps on electrode pads of a semiconductor chip by means of bonding wires and forming a rewiring pattern to be connected to the bumps (see, e.g., Patent Document 1).
[Patent Document 1] JP-A-9-64049
However, under the method described in connection with Patent Document 1 (JP-A-9-64049), when rewiring to be connected to the bumps is formed by means of bonding, there arises a problem of a necessity for adjusting (leveling) the height of the bumps.
For instance, bumps formed by means of bonding wires are formed by use of; e.g., a bonding machine. The bumps are formed by continuously connecting bonding wires from bumps to electrode pads and cutting the bonded bonding wires.
Therefore, the bumps formed by the bonding wires vary in height from a plane where the bumps are formed (i.e., electrode pads). Such variations pose difficulty in forming a rewiring pattern to be connected to the bumps. For this reason, there is needed a step of smoothing bumps by means of exerting a predetermined weight to the bumps.
Smoothing of such bumps is usually performed on a wafer scale (before separation of a chip into pieces by means of dicing). However, in the case of a wafer which has a diameter of 300 mm and which has recently become predominant, when a plurality of bumps formed within a wafer plane are smoothed, there arises a problem of an increase in variations in the height achieved after smoothing.
For instance, when variations in the height of the bumps have increased, variations arise in the state of a connection between the rewiring pattern to be connected to the bumps with the bumps, which in turn raises a problem of deterioration of the reliability of a semiconductor device (a package).
Moreover, under the method described in connection with Patent Document 1 (JP-A-9-64049), an insulating layer is formed so as to cover the bumps. Hence, there has become required a step for abrading the insulating layer in order to make the bumps exposed. In order to form a rewiring pattern after abrasion step, processing for roughening the surface of the insulating layer (so-called desmear processing) is required when an electroless plating technique is used. As a result, processing for forming a plating layer becomes complicated. This in turn adds to the cot for manufacturing a semiconductor device (a package).
Forming a conductive layer by means of sputtering or CVD is also practicable. However, the method requires an expensive film growth apparatus having a vacuum processing container, which also adds to manufacturing cost. Thus, the method is not realistic.